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Altera_Forum
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9 years ago

Edge detection asynchronous signal fails

Hello, I am working on a fairly simple VHDL design where I am trying to detect the rising_edge of an input. Whenever a rising_edge is detected I want to multiply another input by 2 and output ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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Unfortunately my earlier statement was wrong. I still see glitches with the synchronous code above. Here is the output from my test bench:

https://www.alteraforum.com/forum/attachment.php?attachmentid=13378

Is that normal?

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Well, now that I think about it. I guess it does not matter since my_output is stable at the next rising_edge. Before that my_output is not read by any other component.