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Honored Contributor
Honored ContributorEdge detection asynchronous signal fails
Hello, I am working on a fairly simple VHDL design where I am trying to detect the rising_edge of an input. Whenever a rising_edge is detected I want to multiply another input by 2 and output ...
Altera_ForumHonored Contributor
Honored ContributorI think what causes confusion to beginners is the term "edge detection".
We are used to think of "edge" as clock rising or falling edge. For other signals(apart from clock) we can't detect rising or falling edge but we want to identify the first transition pulse (that extends over one clock period). It is better defined as rising sample.
