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To perform gate-level timing simulation, the ModelSim or ModelSim-Altera software
requires information about how the design was placed into device-specific
architectural blocks. The Quartus II software provides this information in the form of
a *.vo file for Verilog HDL designs and a *.vho file for VHDL designs. The
accompanying timing information is stored in the *.sdo file, which annotates the
delay for the elements found in the *.vo file or *.vho file.
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from the Quartus II Handbook section on ModelSim:
http://www.altera.com/literature/hb/qts/qts_qii53001.pdf
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