Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
19 years ago

EDA gate level simulation

when i do a timing simulation using Quartus (and not third party EDA tool), i am able to notice all the delays like the output changing some time after the positive edge of clock (which in a functional simulation wud change exactly at the positive edge of clock).

however, if i try to run gate level simulation using modelsim as third party tool from within quartus, i donot see these delays.

there exist two options - rtl simulation and gate level simulation. i believe rtl simulation is just a fucntional simulation while gate level simulation shud take into account the timing information. but it seems that even for gate level simulation, i am getting the same behavious as that for rtl simulation. the maximum freq on which my design can work correctly is 145 MHz (as the timing analysis of my design in quartus reports).

now, even when i set the clock in my testbench to 1GHz and run gate level simulation, the modelsim simulation gives correct results. (timing simulation within quartus wont give correct result for this, but we cannot use a testbench in quartus simulation so I am using modelsim).

any ideas?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    Are you correctly using the .sdo file with SDF timing information? The .sdo file is generated by Quartus in the same directory where it puts the ModelSim .vo or .vho gate-level netlist file.

    In Quartus on-line help contents, look at "Integrating Other EDA Tools --> Using Other EDA Simulation Tools --> About Using the ModelSim Software with the Quartus II Software --> Performing a Timing Simulation with the ModelSim Software".
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    If you don't see any delay in timing simulation, there is a possibilty that your SDO file is not annotated correctly during timing simulation. How do you run the simulation? Try to use the native link feature (Tools->EDA Simulation Tools -> RUN EDA Gate Level SImulation) as a reference whether you setup the *.do script correctly or not. Do you still get zero delay using native link? This is unlikely.

    Refer the native link feature at http://www.altera.com/literature/hb/qts/qts_qii53001.pdf for more information.