easy way to connect things?

If I've done this right I've added an attachment VHDL file named new_test_top.vhd.

It is a top level design with a reasonably good example of combining lower level designs together, it even includes a call to an EPLL and some top level code.

It's a pretty basic example of hierarchical designing in VHDL.

Most of the COMPONENTs are user generated lower level designs. For all the signals that are to interface to other COMPONENTs you declare them as SIGNALs. For the SIGNALs that are inputs or outputs they are called such at the top-level ENTITY. For those SIGNALs that both go to outputs and to other COMPONENTs you must rename something and direct them appropriately.

As you can see I tend to follow a rather strict formatting of my code to try and make it easier to follow. You don't need to follow such a strict format, you just need to follow the allowed VHDL coding rules.

I hope you can get this.