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Altera_Forum's avatar
Altera_Forum
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13 years ago

Easy way to attach address and data bus to the outside world ?

Hi All,

An SPOC NIOS controller has been built in Verilog that includes SDRAM, and an instance has been added to a top level block schematic.

The NIOS controller exposes about 40 signals associated with the SDRAM that need connection to the real world through I/O pins.

While not being entirely averse to the prospect of spending the next day dragging and connecting 40 odd wires, I can't help thing that some clever bugger who designed Verilog, or built Quartus had some much more cunning-plan to manage the connection of buses to the outside world.

Any wisdom appreciated.

-Mark

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Given that you're living in the dark-ages of using block diagrams, then you only have yourself to blame :)

    If you also code the top-level in Verilog, you're done, you just need a Tcl script with the pin constraints.

    Take a look at this tutorial, it has an SOPC/Qsys system integrated with a top-level design, along with simulation and synthesis scripts:

    http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    You could instantiate your system with verilog rather than block diagrams (no dragging & connecting wires necessary). Then "connecting" a signal is simply typing in the signal name to the port name. For assigning pins, you can either do it one by one in the pin planner, or import pin assignments from another project where it was done previously.

    EDIT

    Ah, someone beat me to it :)

    Best,

    Rob
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Thanks guys.

    Is it possible to access I/O pins from a subordinate Verilog block, or does all I/O have to de done at the top level ?

    -Mark
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    You'll need to route them as wires/signals to your submodules. Top level should interface with the outside world, so to speak.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hi Mark,

    --- Quote Start ---

    Is it possible to access I/O pins from a subordinate Verilog block, or does all I/O have to de done at the top level ?

    --- Quote End ---

    In simulation you can access signals anywhere within the design. However, for synthesis, the signals that route to pins have to be part of the top-level entity.

    However, with SignalTap II (Altera's logic analyzer) you can probe pretty much any signal within the design.

    For example, you can use Modelsim for design and simulation, and then SignalTap II to confirm your logic in hardware.

    Cheers,

    Dave