Early Place stage in Quartus flow

The Early Place feature has been removed from Quartus version 20.1 onward as it is of little value to most users so I don't really recommend to use it.

Early Place :

Begins assigning core design logic to device resources. After this stage, the Chip

Planner can display initial high-level placement of design elements. Use this

information to guide your floorplanning decisions.

Start Fitter (Place) :

Completes assignment of core design logic placement to device resources

Reference:

https://people.ece.cornell.edu/land/courses/ece5760/DE1_SOC/qts-qpp-handbook.pdf

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey.