Early Pin Planning (without HDL)

HDL isn't much trouble for what you're trying to do. All you need is a black box of the design with just the port names and port directions (for example, an empty module in Verilog with just the port list). You can mix that method for your big buses with Reserve Pin assignments for other pins if you want, but I'd use the black box HDL file to tell Quartus all the pin names and directions.

After creating the black box HDL file, Analysis & Elaboration is enough to access the pin names in the Pin Planner. After the pin locations and I/O standards are entered, run Analysis & Synthesis and I/O Assignment Analysis.

Later you can start adding things like PLLs to the HDL file to tell Quartus what is happening on clocks for more thorough checks of pin placement restrictions. You can add some dummy logic to keep the clocks from synthesizing away, or you can add black box HDL placeholders for the lower-level blocks of the design and use incremental compilation empty design partitions for them until you're ready to write the real HDL for those blocks.

If you still prefer Reserve Pin assignments, set up the Assignment Editor window with one example entered. Do "File --> Export" to create a .csv. Modify the spreadsheet in Excel to add rows for the rest of the pins. With the Assignment Editor window selected, do "Assignments --> Import Assignments".

If there's a trick to do what you want with the Assignment Editor Edit bar, maybe someone will post that here.