Duty cycle VHDL

Hi Frans

Infact your code simply creates a 50/50 square wave.

I think this is what you need:

library altera;
library IEEE;
use IEEE.std_logic_1164.all; 
use IEEE.numeric_std.all;    -- for the unsigned type
entity pwm_generator is
	port (CLKIN   : in  std_logic;  
		  TPERIOD : in  unsigned(7 downto 0);   
		  TWIDTH  : in  unsigned(7 downto 0);   
			PWM   : out std_logic );
end entity pwm_generator; 
architecture pwm_gen_a of pwm_generator is
	subtype small_int is natural range 0 to 500;
	begin  
		update: process(CLKIN) is  
		variable tcnt : small_int := 0;
		begin
			if rising_edge(CLKIN) then  
				tcnt := tcnt + 1;
				if tcnt = TPERIOD then
					tcnt := 0;
				end if;
				if tcnt >= TWIDTH then
					PWM <= '0';
				else
					PWM <= '1';
				end if;
			end if;  
		end process;   
	end architecture pwm_gen_a;

You may need to change TPERIOD and TWIDTH bit length to meet your specs.

You must also add the pwm switching function.