During “Analysis & synthesis”, the Quartus Pro 17.1.2 Build 304 (Patch 2 installed) can’t recognize and load the right “.mif” file which is already specified in the VHDL code via the "attribute ram_init_file".

Hi, Sorry for late reply. I am requesting the help from internal team, as suspect it is internal bug. They might need sometime to look at it. Btw, is this possible for you to run your design using quartus version 18.1.1 as we encourage customer to use the latest version. Thanks Joanne