can I do something like this ?
many thanks!!!!
1. ARCHITECTURE
-------------------------------
COMPONENT pulser
-------------------------------
PORT
(
hifu_hv_pw :in std_logic_vector ( 7 downto 0 ) --0->15 hifu_pw
);
END COMPONENT;
2.ARCHITECTURE
type m0 is array (1 downto 0) of std_logic_vector(7 downto 0);
signal array_pw: m0 ;
3. BEGIN
hifu_hv_pw0<="01010101";
hifu_hv_pw1<="11111111";
array_pw <= hifu_hv_pw1 & hifu_hv_pw0 ;
4. PORT MAP
puls : for n in 1 downto 0 generate
pulser_port:pulser
port map
(
hifu_hv_pw => array_pw(n)
);
end generate puls;