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Same here. I'm using a EP4C115F23C8 with Quartus II 10.0 SP1. As recommended, I added the following lines to the .qsf file:
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
With SignalTap I can see the correct waveforms on FLASH_CE#, DCLK and ASDO, but DATA0 is always high.
If I measure on the hardware, I see the corresponding waveforms on FLASH_CE#, ASDO and DATA0.
but dclk is always high (all signals have external pull-ups). As DCLK behaves differently between SignalTap and hardware, I assume that the DCLK FPGA Pin actually is in high-impedance state.
The Pin-Out File tells this:
Pin Name/Usage : Location : Dir. : I/O Standard : Volt. : Bank : Usr. ***.
Fpga_Dclk : K2 : output : 3.3-V LVCMOS : : 1 : Y
So one could assume that everything is ok, but it obviously is not. Going back to Quartus 9.x is no option because the 9.x EPCS Flash Controller does not work with Cyclone IV devices. Any ideas around?
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The mistery seems to be resolved. The user design can't use the DCLK pin as an output if the Cyclone IV has been programmed in PS mode. If AS mode has been used for programming, the DCLK output works just fine with the EPCS controller. So, if using PS mode, one might consider connecting the EPCS clock signal to a user I/O instead of the DCLK pin (which actually worked in my case).
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