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Look at that. I suppose I had never been actually using the dpram models for dual-write purposes. This sure is a shame.
I knew that driving the same signal from different processes was an issue for synthesis, but I thought simulation would resolve down to the address location and not just the signal itself.
Does Altera have any intention on fixing this, or is their solution to instantiate an altsyncram?
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Even with altsyncram instantiation, it requires two clocks to read two different addresses simult., which is a draw back that makes dual-port same like single-port ram in that point :( .
Also, the ram array inside the altsyncram is declared as a variable in a process, which prevents u from seeing it in modelsim, which makes debugging very difficult if u want to see the contents of the ram at any instant of time.
This was not the case with the template usage, where the ram array was declared as a signal.
Anybody has a solution to this?
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