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I am a little confused by this. I use something extremely similar to the template for my synthesis and simulation models and don't seem to have any issues. Writing to the same address should cause contention, but as long as each port is writing to different addresses, it shouldn't be an issue. Right?
I also am not sure what you mean by having the writes in the same process would imply a priority. Using two separate if-statements and testing on the write enable signal should, effectively, be the same thing - shouldn't it? I realize it doesn't get synthesized by Quartus II as a RAM, but behaviorally is it any different in simulation?
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This is my original problem; that two if-statements checking on 2 write enables in two separate processes are synthesised successfuly to RAM blocks, however, simulation on Modelsim gives X contention when writing to the 2 ports simultenously as HDL Guru said, even if writting to different addresses.
If the two if-statements are put in one process, then this acts behaviorly right on the simulator, however, it's not synthesised to RAM blocks as u said.
It seems that this is a problem in the template itself.
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