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This is a known problem with the dual-port RAM template. It has two process statements that write to the same signal (a 2-D array of std_logic, a resolved type). When both process statements drive the signal, it results in logic contention that shows up as X.
Unfortunately, the template can't use a shared variable because Quartus II doesn't infer RAMs from shared variables. It also can't move the two writes into the same process because that would imply a priority between the two writes that doesn't exist in the underlying hardware.
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I am a little confused by this. I use something extremely similar to the template for my synthesis and simulation models and don't seem to have any issues. Writing to the same address should cause contention, but as long as each port is writing to different addresses, it shouldn't be an issue. Right?
I also am not sure what you mean by having the writes in the same process would imply a priority. Using two separate if-statements and testing on the write enable signal should, effectively, be the same thing - shouldn't it? I realize it doesn't get synthesized by Quartus II as a RAM, but behaviorally is it any different in simulation?
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