Dual port RAM in Quartus II 7.2, different behavior on ModelSim than Quartus simulato

Thanks for ur useful replies

I'm only testing the template without any code on top of it, so i just wrote a test bench which instantiates "true_dual_port_ram_single_clock" and drive it in a clk synch. process (rising edge) to write X"5A5A" in addresses that r incremented inside the same process, so all transitions are clk synchronized.

And it's clear on the ModelSim simulator that the memory is initialized with zeros not 'X', where a memory initialization file (.MIF) is created for this purpose during synthesis to altsyncram, and it seems that ModelSim is aware of this file, since it's affected by modifications in it, which makes me feel that the altsync ram synthsis is communicated to ModelSim somehow. There's a file (.vho) automatically created in the simulation/modelsim folder that contains an auto generated code of my test bench with instantiation of altsyncram, i think ModelSim uses this file.

I'm currently trying direct instantaition using megafunction (hope it works), however, I dont prefer this solution for the sake of portability :(