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Altera_Forum
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15 years ago

Dual-Port Ram Implementation Questons

Hello everybody!

I need to use a Ram block in my project, and I have been experimenting with the Mega-Wizard to implement a Dual-Port Ram block, using M4K On-Chip Memory Blocks.

I have read/studied chapter 7 of the Altera Cyclone Handbook, but there are still a few points I need to clear out.

1) Regarding "aclr" (clear/reset of RAM), I need to implement it Active Low, but I couldn't find such an option. I thought of putting a NOT at the input signal of the Ram Block, but because of Wizard-generated code I'm not sure if this a good idea.

2) I saw that I can specify different data input and output widths, e.g. I need a 16-bit input and an 8-bit output. I couldn't find any description of how this works. Is data outputted serially? Are there any suggestions referring to this?

Thank you in advance!

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    but did you do this?

    data_bus(7 downto 0) <= DATA_IN(15 downto 8);

    data_bus(15 downto 8) <= DATA_IN(7 downto 0);

    or you can just do it directly:

    data_bus(0) <= DATA_IN(7);

    data_bus(1) <= DATA_IN(6);

    data_bus(2) <= DATA_IN(5);

    data_bus(3) <= DATA_IN(4);

    ...etc
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Tricky thank you and sorry about not answering.

    I finally solved it out in a much easier way: I just change the MSByte (!!) with the LSByte in another block of my design (where DATA is actually 'created')!

    I was stuck in the idea of solving it either at the Ram block or at the generated port-map block. Anyway..

    Thanks again for your interest!