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Altera_Forum
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15 years ago

Dual-Port Ram Implementation Questons

Hello everybody! I need to use a Ram block in my project, and I have been experimenting with the Mega-Wizard to implement a Dual-Port Ram block, using M4K On-Chip Memory Blocks. I have rea...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Ok, you were right, didn't find anything in schematic at all!

I tried changing it in the VHDL created top-entity port map file, in quite an easy way.

I split the incoming DATA into two SYNTHESIZED_WIRES, (15 downto 8) and (7 downto 0), and then matched them to the data_bus of the ram block, firstly with concatenation, and then seperately. Unfortunately neither of what I tried showed any result, as in simulation data is still read inversely.

What else can I try?

I appreciate your help!