Forum Discussion
Altera_Forum
Honored Contributor
15 years agoYes that is done in the schematic (assuming you're using the Quartus schematic entry tool.
You cannot connect the links directly, you have to use named nets. I think there is a "group" block so you can regroup busses. All of this is MUCH easier in VHDL or verilog. Its a bit tedious in schematic.