Dual-Port Ram Implementation Questons

1) Ok, I simply put a NOT gate at the schematic, before the signal being input to aclr.

I use an asynchronous reset throughout whole the system, which is active low, that's why I needed it to be the same - so I can assign it the same reset-signal.

The Ram Block is used for buffering raw 16-bit audio samples, which are then encapsulated into UDP packets. Obviously there will be no problem at all if I didn't use aclr. I didn't know about it causing troubles.

2) Actually, because of the Eth_TxD code I'm using, I need to get these 16-bit samples in 8-bit pieces at the output, but with the MSB first (?!).

I got that with the addresses, and I can also clock it elsehow if I want/need to. Does it start with the MSB of the word stored?

I have actually achieved that, but in a less professional way (leaving available the 16-bit output data for twice a time, so I can retrieve the same sample/word twice - e.g. RamOut(15 downto 8) first and then the rest, and so on..), so I'd like to make it look better.

Thank You.