Dual Port RAM acces in VHDL

Hi Daixiwen,

yes you were right. I had a lot of warnings for latches.

I redesigned the state machine to one porcess holding the complete structure.I also added default values before the case statement. Now i do not get the warnings anymore. However what i am still struggling with is multiple reading from different address.

When the control signal master_setup is active, the value in the address 0x10 defines with components get initialized. (state setup_eval_var).

From there multiple variables are read from fixed memory locations and assigned to output ports. ( halfbridge_freq_scale halfbridge_duty)

But here wrong values are read and i do not know why.

When i downscale the system to only one variable everything works fine. So for example reading only halfbridge_freq_scale the system works fine.

The component them self work fine. Simulation with Modelsim or running with constants shows perfect behavior.

Am i doing something wrong with the multiple address incrementation?

    
case state is
    when idle =>                
        if master_setup ='1' then  
            state <= setup_eval_var_addr;
        elsif master_run ='1' then 
            state <= setup_run_addr;
        elsif master_wr ='1' then 
            state <= setup_write_addr;            
        else 
            state <= idle;
        end if;
    
    when setup_eval_var_addr => 
            av_m_clken             <= '1';
            av_m_cs                 <= '1';
            av_m_byteenable     <= X"F";
            av_m_address <=  b"0_0000_0001_0000";
            state <= setup_eval_var;                
    when setup_eval_var =>
            av_m_clken             <= '1'; 
            av_m_cs                 <= '1';
            av_m_byteenable     <= X"F";
            if av_m_rddata = X"00000001" then --read halfbridge vars
                state <= setup_hb_freq_addr;                
            elsif av_m_rddata = X"00000002" then
                state <= setup_dp_t1_addr;
            elsif av_m_rddata = X"00000003" then            
                state <= setup_npc_freq_addr; --tbd
            else
                state <= idle;
            end if;
            
    
-- HALFBRIDGE states for reading the desired signal frequency 
    when setup_hb_freq_addr =>
            av_m_clken             <= '1';
            av_m_cs                 <= '1';
            av_m_byteenable     <= X"F";
            av_m_address <= b"0_0000_0100_0000"; --64
            state <= rd_hb_freq;
    when rd_hb_freq =>
            av_m_clken             <= '1';
            av_m_cs                 <= '1';
            av_m_byteenable     <= X"F";
            halfbridge_freq_scale  <= av_m_rddata;  --output port to halfbridge component 
            state <= setup_hb_duty_addr;
-- HALFBRIDGE states for reading the signal duty cycle value    
    when setup_hb_duty_addr => 
            av_m_clken             <= '1';
            av_m_cs                 <= '1';
            av_m_byteenable     <= X"F";
            av_m_address <= b"0_0000_0001_1000"; --24
            state <= rd_hb_duty;
    when rd_hb_duty =>
            av_m_clken             <= '1';
            av_m_cs                 <= '1';
            av_m_byteenable     <= X"F";
            halfbridge_duty <= av_m_rddata;
            if master_rd ='1' then 
                state <= setup_hb_freq_addr;        
            else
                state <= idle;
            end if;