Dual Port RAM acces in VHDL

You never disable the write signal in your process. This means that you will continue to write values even in the read state. This code should generate a lot of latches warnings, as you aren't assigning values to every signal in every state of your state machine. I suggest that you add some default values before the case statement for every output signal used in the process to avoid this problem. You can use '0' as default value for the control signals (read, write, chip select, byte enable) and just put them to '1' when needed.