Dual Port RAM acces in VHDL

ok me again. Now i have a question about writing and reading from VHDL to memory. I designed a state machine to handel multiple rd/wr to different address locations.

The idea is to write the counter to the first 10 locations. After that it should switch into the read state and stay there forever. There outputs depending to the value i write from C should be toggled.

When i start a memory scan i C i see something in memory but not the desired counter values.

In the read state the ports q1 and q2 work correct only when i write in C to the base_address. But it should be working by writing to the first register so base_address +0x4.

I think i do not really apply the next address to the memory module.

Do you have an idea?

Cheers,

Tim

type state_type is (addr_inc,wr,idle,rd);
signal pr_state, nx_state : state_type;
signal av_m_address_i : std_logic_vector(12 downto 0);
signal k_p : std_logic_vector(31 downto 0);
signal counter : integer := 0;
begin
process(clk, reset)
BEGIN
if reset = '1' then 
    pr_state <= idle;
elsif clk'event and clk ='1' then
    pr_state <= nx_state;
end if;
END PROCESS;
process (pr_state)
BEGIN 
case pr_state is    
    when idle =>
        nx_state <= wr;
        av_m_address_i <= b"0_0000_0000_0000";
        counter <= 0;
    when wr =>    -- increment the counter value and write it to the address
        counter <= counter + 1;
        av_m_write <= '1';
        av_m_clken <= '1';
        av_m_chipselect <= '1';
        av_m_byteenable <= X"1";
        av_m_address <= av_m_address_i;
        av_m_writedata <= std_logic_vector(to_signed(counter,32));
        counter <= counter + 1;
        if counter = 10 then 
            nx_state <= rd;
        else
            nx_state <= addr_inc;
        end if;    
    when addr_inc =>
        av_m_address_i <= std_logic_vector(unsigned(av_m_address_i) + b"0_0000_0000_0100");
        nx_state <= wr;
    when rd => 
            av_m_address <= b"0_0000_0000_0100";
                if av_m_readdata = X"00000000" then 
                    q1 <= '1';
                    q2 <= '0';
                elsif av_m_readdata = X"00000001" then 
                    q1 <= '0';
                    q2 <= '1';
                else    
                    q1 <= '1';
                    q2 <= '1';
                end if;
            nx_state <= rd;
    when others =>
        nx_state <= wr;
end case;
END PROCESS;
end behave;