Dual Port RAM acces in VHDL

I first tried to deactivate the cache then after changed the memory to tightly coupled memory but it still did not work. What i did not do from the beginning was setting the clken bit to one. And that finally solved my problem now i can write to RAM through VHDL. I neglected it because i read that this signal cannot be used in dual port mode with a single clock. I assume this assumtion is wrong but i did not find an explainationo for this type in the avalon spec or in the on-chip memory implementation manual. Could you explain it? Thank you two, helped me a loot :)