Dual Port RAM acces in VHDL

The new code shown will write the value 0x0000000C to address 0 continuously.

In the code:

else
				q <= '0';
				--if ( av_m_read_n = '0'  and av_m_address = b"0" ) then      
				--av_m_readdata <= reg_temp;
				--elsif ( av_m_write = '0' and av_m_address = b"1" ) then  
				av_m_write      <= '1';
				av_m_chipselect <= '1';
				av_m_byteenable <= "1111";
				av_m_address    <= b"0_0000_0000_0000";
				av_m_writedata  <= X"0000000C";
				av_m_address    <= b"0_0000_0000_0001";
				av_m_writedata  <= X"0000000C";
				av_m_address    <= b"0_0000_0000_0010";
				av_m_writedata  <= X"0000000C";
				av_m_address    <= b"0_0000_0001_0000";
				av_m_writedata  <= X"0000000C";
				av_m_address    <= b"1_1111_1111_1111";
				av_m_writedata  <= X"0000000C";
				--av_m_address <= b"0_0000_0000_0011";
				--av_m_writedata <= X"0000000C";
				av_m_write      <= '0';
				av_m_chipselect <= '0';
				av_m_byteenable <= (others => '0');
			end if;

the synthesiser will only honour the 'last' assignment for each signal, thus of al the address assignments in the above code :

				av_m_address    <= b"0_0000_0000_0000";
				av_m_address    <= b"0_0000_0000_0001";
				av_m_address    <= b"0_0000_0000_0010";
				av_m_address    <= b"0_0000_0001_0000";
				av_m_address    <= b"1_1111_1111_1111";

only the very last will be synthesised as it 'wins'.

If you want to do multiple writes you have to do a write per clock cycle and you have to understand sequential coding: I suggest you read pages 91-121 of V. Pedroni's book "Circuit Design with VHDL".