Dual Port RAM acces in VHDL

I aligned the compare value to the databus width and now reading works perfectly !!

But i still do not understand why i cannot write.

At the beginning of the process i assigned the control signals, then the address where i want to write and then the data.

After all the transfers i set the control signals to zero. But is this sequential approach correct?

I thought the RTL viewer shows only the last state of the signals, so the values are actually ok.

When i keep the control signals all the time on high level the RTL shows the correct assignments, but the memory is still empty.

https://www.alteraforum.com/forum/attachment.php?attachmentid=8987

avalon_if : process (reset_n, clk)  
begin
			
	elsif clk'event and clk ='1' then
		av_m_write <= '1';
		av_m_chipselect <= '1';
		av_m_byteenable <= "1111";
		av_m_address <= b"0_0000_0000_0000";
		av_m_writedata <= X"0000000C";	
	end if;
end process avalon_if;