--- Quote Start ---
Ok as an attachment i uploaded the archived project. i hope this makes it clearer.
--- Quote End ---
Yes, that helps ...
Now there are a few issues with the Memorymaster.vhd code:
avalon_if : process(reset_n, clk)
begin
if (reset_n = '0') then
av_m_address <= (others => '0');
av_m_write <= '0';
av_m_read <= '0';
av_m_writedata <= (others => '0');
elsif clk'event and clk = '1' then
--av_m_address <= (others => '0');
--av_m_address(26) <= '1';
av_m_address <= b"0_0000_0000_0000";
if (av_m_readdata = x"F") then
q <= '1';
else
q <= '0';
--if ( av_m_read_n = '0' and av_m_address = b"0" ) then
--av_m_readdata <= reg_temp;
--elsif ( av_m_write = '0' and av_m_address = b"1" ) then
av_m_write <= '1';
av_m_chipselect <= '1';
av_m_byteenable <= "1111";
av_m_address <= b"0_0000_0000_0000";
av_m_writedata <= X"0000000C";
av_m_address <= b"0_0000_0000_0001";
av_m_writedata <= X"0000000C";
av_m_address <= b"0_0000_0000_0010";
av_m_writedata <= X"0000000C";
av_m_address <= b"0_0000_0001_0000";
av_m_writedata <= X"0000000C";
av_m_address <= b"1_1111_1111_1111";
av_m_writedata <= X"0000000C";
--av_m_address <= b"0_0000_0000_0011";
--av_m_writedata <= X"0000000C";
av_m_write <= '0';
av_m_chipselect <= '0';
av_m_byteenable <= (others => '0');
end if;
end if;
end process avalon_if;
The line:
if (av_m_readdata = x"F") then
will always return false as 'av_m_rreaddata' is wider than the width of x"F"
From the lines:
av_m_write <= '1';
av_m_chipselect <= '1';
av_m_byteenable <= "1111";
av_m_address <= b"0_0000_0000_0000";
av_m_writedata <= X"0000000C";
av_m_address <= b"0_0000_0000_0001";
av_m_writedata <= X"0000000C";
av_m_address <= b"0_0000_0000_0010";
av_m_writedata <= X"0000000C";
av_m_address <= b"0_0000_0001_0000";
av_m_writedata <= X"0000000C";
av_m_address <= b"1_1111_1111_1111";
av_m_writedata <= X"0000000C";
--av_m_address <= b"0_0000_0000_0011";
--av_m_writedata <= X"0000000C";
av_m_write <= '0';
av_m_chipselect <= '0';
av_m_byteenable <= (others => '0');
only the very last assignments
av_m_address <= b"1_1111_1111_1111";
av_m_writedata <= X"0000000C";
av_m_write <= '0';
av_m_chipselect <= '0';
av_m_byteenable <= (others => '0');
will be synthesized and you are inherently not writing into the DPRam, so the NIOS II will not read anything other then the data initialized at start-up which will be all zeroes after loading the sof (unless you specify a .mif file with user-data)
You can see in the attached RTL-snip what the Synthesizer made out of your .vhd source.
Honored Contributor
