Dual Clock FIFO Implementation VHDL

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I'm not 100% sure, but I think variables don't map to physical wires or registers, but I could be wrong (I never use variables for the purpose you use it for). Use a variable as a "helper" only, not for things that must be remembered between clocks. All of your variables should map to signals.

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Variables can map to anything that signals can map to. But it can be less obvious what that may be. Hence why it is highly recommended that you use signals for everything. There is nothing you cant do with a signal (for logic implementation).