Dual Clock FIFO Implementation VHDL

Hi,

there are a lot of peculiarities about your code; nothing out of the common when you say you're new with VHDL, though.

The following changes are recommended, some even necessary:

• use signals instead of variables

• make sure each signal is only accessed by a single clock

• only use one clock/reset-sensitive IF per process

I'm not 100% sure, but I think variables don't map to physical wires or registers, but I could be wrong (I never use variables for the purpose you use it for). Use a variable as a "helper" only, not for things that must be remembered between clocks. All of your variables should map to signals.

Then, look at "Looped". Its written both on the rising edge of ReadCLK, and on the rising edge of WriteCLK. Maybe other signals have this problem too, I didn't look into it that deep. That's my second point in my above list.

Then, for the sake of clarity: use one process per clock, i.e. the following pattern always applies:

process(rst, clk) is
begin
  if(rst = '1') then
    -- reset code
  elsif(rising_edge(clk)) then
    -- synchronous code
  end if;
end process;

This is the pattern that you will find almost anywhere, and everybody familiar with VHDL will understand it. Multiple clocks per process just lead to confusion.

Also, the sensitivity list of your process is wrong. It should contain the reset and the clock, and only those. Your code won't simulate correctly.

Finally, since you're going to implement a dual-clock FIFO, you need to learn about synchronization between crossing clock domains. I can't see any. Such FIFOs are typically built with gray counters, to avoid problems, and proper synchronization is a must. Just google about "VHDL clock domain crossing". Or just google for dual clock FIFOs and see how they do it. Without that understanding, your FIFO will work perfectly in simulation, and most of the time perfectly in reality, but sometimes just mess up your data.

Best regards,

GooGooCluster