Don't think so, named it asynch_fifo in subfolder fifo.
Main design instantiates asynch_buf.v:
// ==========================================================================
// Asynchronous buffer
// --------------------------------------------------------------------------
// The high-speed LVDS clocks rx_clk and tx_clk are synchronous but
// off-phase, thus the buffer should maintain constant size.
// ==========================================================================
assign asynch_buf_reset_n = reset_n && opt_done;
asynch_buf async_buf_i ( .data ( rx_data ),
.rdclk ( rx_clk ),
.wrclk ( tx_clk ),
.reset_n ( asynch_buf_reset_n ),
.q ( tx_data ) );
And asynch_buf instantiates asynch_fifo.v:
module asynch_buf ( input data,
input rdclk,
input wrclk,
input reset_n,
output q );
// +-----------------------------------------------------------------
// | Internal signals
// |
// +-----------------------------------------------------------------
wire rdempty;
wire rdusedw;
wire wrfull;
wire wrusedw;
// +-----------------------------------------------------------------
// | Write Request
// | * Active when not in reset
// +-----------------------------------------------------------------
reg wrreq;
always @(posedge wrclk, negedge reset_n)
begin
if ( !reset_n )
wrreq <= 0;
else
wrreq <= 1;
end
// +-----------------------------------------------------------------
// | Read request
// | * Active when data is available
// +-----------------------------------------------------------------
wire rdreq;
assign rdreq = !rdempty;
// +-----------------------------------------------------------------
// | Asynchronous FIFO
// |
// +-----------------------------------------------------------------
asynch_fifo asynch_fifo_i( .data ( data ),
.wrreq ( wrreq ),
.rdreq ( rdreq ),
.rdclk ( rdclk ),
.wrclk ( wrclk ),
.q ( q ),
.rdempty ( rdempty ),
.rdusedw ( rdusedw ),
.wrfull ( wrfull ),
.wrusedw ( wrusedw ) );
endmodule
It's a mystery. I also tried to generate the FIFO again, no luck... Any ideas?
[EDIT]
Added megafunction generated verilog file
Honored Contributor
