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Altera_Forum's avatar
Altera_Forum
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10 years ago

DSP usage issue with arria10

The following circuit is designed to fit in 2 DSPs on StratixV FPGA: http://www.alteraforum.com/forum/attachment.php?attachmentid=11892&stc=1 -> a,c,e and g are input ports (signed) -> ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

At first glance, I cant really understand why. It could just be a compiler bug with inference ie. you're not quite using the template expected. have you tried using separate intermediate signal outside of the clock process for the multiplication and addition, with only the final register in the process? Have you tried using intermediate variables instead?

I suggest raising a ticket with altera's mysupport.