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Altera_Forum
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18 years ago

DSP Builder and Signal Tap II

Hi, I have some simple questions. I working on an Altera DE2 with a Cyclon II FPGA inside. I'm doing some simulation with the DSP Builder like simulate a stair signal ora a Sinewave ...
Altera_Forum's avatar
Altera_Forum
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17 years ago

The discussion has been regarding requirements for a suitable acquisition clock. It's not said, that you can't use a gated clock at all. It may work, although the timing is probably not perfect. I often use it as a quick and dirty solution. Alternatively you can use segemented trigger to acquire data at a reduced rate. If I understand right, Quartus 8 has new options in this regard, but I didn't evaluate them yet.