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Altera_Forum
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18 years ago

DSP Builder and Signal Tap II

Hi, I have some simple questions. I working on an Altera DE2 with a Cyclon II FPGA inside. I'm doing some simulation with the DSP Builder like simulate a stair signal ora a Sinewave ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Hi all,

Sorry but I don't understand the workarounds at all :(

I have similar problem, I try to check correction of data from audio codec with signaltap on 2S60 DK.

How can I decrease rate of data assigns to signaltap memory.

Thank you in advance.

yan_w