DSP Builder and Signal Tap II

Hello,

using a derived clock for Signal Tap most likely causes timing problems und incorrect signal acquisition. Anything that is said regarding not to use derived clocks in design also applies to Signal Tap. Signal Tap should be clocked by the design's under test main clock. A PLL generated divided or multiplied clock can also give good results. "Acquisition doesn't stop" sounds like there is no real clock at all. A simple way to get a slow signal tap aquisition is with a derived clock as trigger for segmented x 1 acquisition mode, but you don't have another trigger then and can do only free-running acquisition.

Regards,

Frank