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Altera_Forum
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18 years ago

DSP Builder and Signal Tap II

Hi, I have some simple questions. I working on an Altera DE2 with a Cyclon II FPGA inside. I'm doing some simulation with the DSP Builder like simulate a stair signal ora a Sinewave ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

I've just put my DE2 board block in the schematics, so are there no other assignements to do more then the ones in the board block? Also if I use the clock block? And also if I use the clock derived block?

I think to have solved the problem anyway. I think that the problem was in using a derived clock for the signal tap so I 've used the base clock for the SIgnal Tap and I've speeded up the simulation with a PLL clock.

The manual is not really clear about PIN assignement and clocks...