DSP Block Balancing settings using OpenCL

Thanks for your comment. I reran some synthesis and have some updates. I realized the change from DSP to logic happened when I did change something in the kernel A which I thought should not have an effect. I put a loop unroll pragma before one of the loops but passed 1 as the parameter, which essentially shouldnt unroll the loop. I added that only for later experiments with kernel A but didnt think it would have an effect for other experiments if I keep unroll as 1. However it did and used logic instead of DSPs and reverted back to DSPs if I removed the pragma.

The loop has some integer additions and one integer multiplication, compiling for Stratix V. I am not sure why is it happening but for now I will just remove the unroll pragma as it is not absolutely necessary.