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Do not do a generic 4:1 mux in logic. That could get synthesized in a way that makes glitches. Build a 2:1 mux and keep attribute on the output signal/wire.(Open the HDL file in Quartus and go to Edit -> Insert Template -> VHDL or Verilog -> Synthesis Attributes for details on keep. This means the clock will only feed one LUT at a time. Synthesis has an uncanny way of making your 4:1 mux smaller/faster, which is good for general logic, but too often results in the clock feeding two LUTs at once, and results in glitches.
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Hi,Thank you very much for your suggestion!
Actually your suggestion is very important to me !
Now what I am going to do is to create several clock signals using PLL and feed them to the CPU clock(this is because I need to change the CPU frequency dynamically during runtime for research purpose) . I use fixed clock for other components in SOPC(such as SDRAM) and then I use clock bridge to connect them to the CPU.
I am trying to use PIO to control the multiplexier during the runtime to change the CPU clock input.
So your suggestion is that if I want to use 4 clocks ,I 'd better use 3 2-input mutiplexier rather than 1 4-input mutiplexier and change some thing in the systhesis option as you told me ( actually I am not quite understand your words about how to change the option but I will try).
Thanks very muck!
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