Forum Discussion
Altera_Forum
Honored Contributor
8 years agoUsually that would be due to missing timing constraints, but I see you are connected to on-chip rather than off-chip flash.
I it seems you assigned the memory region in the BSP editor, but did you change the physical wiring in Qsys to allow Nios II instruction/data master to access the on-chip flash? (I can't see the Qsys diagram...resolution too small...)