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Altera_Forum's avatar
Altera_Forum
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18 years ago

down counter

y guys,

I have to code for the down counter. As u know , the down counter will take the data in put when the load is high( level trigger) and then when the load is low , they start to count down which is control by the "clock" . As i know is the "load" will be level trigger and the clock will be edge trigger.

The thing is , usually my frequency of the load usually less than the clock . For example , if i have the load frequency is 10khz , and suppose my data is 3 bits , then the clock frequency will be 2^3 * 10khz. It help me every (f= 10 khz) to take the data and then count down .

So the problem i facing is since the load is level trigger , then the counter start to count if the load is logic high----> some edge trigger clock , data wont count dow ---> that is not what i want.. I want it they load the data in and then the next cycle of the clock , they start to count down . ( to make sure that every value data load in , they will count down and reach zero)

Some suggestion is "load" signal , not using the 50% duty cycle, but then if i have 8 bits data , then the clock will be 2^8 times the load , then the load will be very small duty cycle.

So i create the new code , to procuce the signal S1 to act like the load signal. But there is some warning about " Timming analysis is analysing one or more combinational loop as a latch ( which is tmp signal in the below code)"

and " found 3 nodes in clock path at the ripple or gate clock..."

Here is the code : the S: load signal and C is the clock signal, D is datain , Q is data out

process (s, c) is

begin

if c'event and c = '0' then

s2 <= not s;

end if;

end process;

s1 <= s and s2;

process (s1, c, d)

begin

if s1 = '1' then

tmp <= d;

elsif (c'event and c= '1') then

tmp <= tmp - 1;

end if ;

end process;

q <= tmp;

end behavioral;

I use the quartus II software. I am new in VHDL .

Another problem , in this code i also want to take the S1 out , that is why i declare it as inout . So i can create the symbol for this code , and the use in the schematic. But when i run the compile , there is one warnning : " S1 is missing source signal" . How can i overcome it ?

Regards.

clark

Regards

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Hello Clark,

    I think, using an asynchronous load isn't a good solution. You should try to do the load operation within the C'event respectively rising_edge(C) action. If your load signal is too long, you can use edge detection. At first step, I would try without an inverted clock (no action at falling_edge(C) ).

    It is important to know, if S is synchronous to C (has defined setup and hold timing). Otherwise, the counter may sometimes load unexpected values. An asynchronous load signal should be synchronized to clock first. Basically this hasn't anything to do with HDL programming, the effects are present with discrete logic as well.

    What's the best solution depends on load signal timing related to clock. I don't know exactly from your posting.

    As a simple VHDL question: To connect an internal signal as output port, you can declare it as buffer or use a wire signal as you did with Q.

    Regards and Happy New Year!

    Frank