Forum Discussion
Altera_Forum
Honored Contributor
11 years ago --- Quote Start --- No, Qsys only knows std_logic_vectors. Actually under the cover Qsys uses Verilog. So if you use (as I do) custom types in your Qsys blocks you will have to write the 2 necessary conversion functions: to_std_logic_vector( t : my_vhdl_type ) return std_logic_vector and its companion to_my_vhdl_type( v : std_logic_vector ) return my_vhdl_type. If you put the definitions of the type and the functions in a VHDL package you can use them throughout your Qsys components. --- Quote End --- Thanks for the quick reply and for the information. I was able to work around this by creating conversion functions.