Does QII support verilog string parameters?

Question

I'm confused..

I admit to not being an expert on all things verilog (or anything in life for that mater), but I am trying to learn to parameterize a new module definition to expand its usefulness without undue added complexity... (what else are parameters for??)

I've googled and found conflicting evidence whether or not verilog supports string-type parameters.. I've seen googled references showing syntax like this:

--- Quote Start ---

module my_module (

parameter string my_name = "BOB" from {"BOB", "SAM"};

[...]

--- Quote End ---

Which looks to be an enumerated type parameter to allow the compiler to infer integer representations for human-readable values ... cool...

But QuartusII (v7.2 sp3) no likey-likey....

--- Quote Start ---

Error (10170): Verilog HDL syntax error at [file](36) near text "parameter"; expecting ")", or ",", or ".", or an identifier ("parameter" is a reserved keyword ), or "{", or "input", or "output", or "inout", or "(*"

--- Quote End ---

Any ideas on enumerated type / string parameters in verilog (2001) using QII?

thanks!

..dane

altera_forum · Answer

Duhhh... I was putting it in the wrong place .... should be defined this way:

--- Quote Start ---

module my_module (

input ...

output ...

);

parameter string my_name = "BOB" from {"BOB", "SAM"};

[...]

--- Quote End ---

Now I need to figure out how to restrict the module instantiation values to predefined values (that I support) and otherwise throw an error...

..dane

altera_forum · Answer

The parameter definition as shown isn't correct Verilog syntax. A module parameter can either appear in a module_parameter_portlist,

#( parameter_declaration { , parameter_declaration } )

or as a module item in module body:

parameter probe_width = 1;

Furthermore, string isn't a defined Verilog type, and typified string parameters are not provided by the Verilog standard. It may be a vendor specific extension?

Altera Verilog IP are using untypified string parameters, e. g.:

parameter instance_id = "UNUSED";

altera_forum · Answer

Yes, sorry, I just copy/pasted and did not correct the syntax of the actual parameter definition ...

But the question now, is, can I create an enumerated list of "supported" values, so that when instantiating within a QII schematic file and they double-click on the module parameter name it provides a drop-down list of acceptable values?

..dane

altera_forum · Answer

I've little knowledge of the schematic editor's interaction with HDL design files. I know, that symbol parameters are controlling VHDL generics respectively Verilog parameters. But I haven't yet seen an example utilizing the drop-down selection in symbol parameters. Personally I stopped using schematic entry some years ago.

The schematic editor is treated as legacy stuff in Quartus Handbook under quartus ii design flow for max+plus ii users and rather briefly documented.

altera_forum · Answer

The string data type is a SystemVerilog feature and currently not supported by Quartus II, even for constants such as parameters.  That's unfortunate because you can only pass around and manipulate strings as a sequence of bits in regular Verilog.

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Does QII support verilog string parameters?

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