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Altera_Forum's avatar
Altera_Forum
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17 years ago

Does QII support verilog string parameters?

I'm confused.. I admit to not being an expert on all things verilog (or anything in life for that mater), but I am trying to learn to parameterize a new module definition to expand its usefulne...
Altera_Forum's avatar
Altera_Forum
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17 years ago

The parameter definition as shown isn't correct Verilog syntax. A module parameter can either appear in a module_parameter_portlist, 

#( parameter_declaration { , parameter_declaration } )

or as a module item in module body: 

parameter probe_width = 1;

Furthermore, string isn't a defined Verilog type, and typified string parameters are not provided by the Verilog standard. It may be a vendor specific extension?

Altera Verilog IP are using untypified string parameters, e. g.: 

parameter instance_id = "UNUSED";