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Altera_Forum's avatar
Altera_Forum
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17 years ago

Does QII support verilog string parameters?

I'm confused.. I admit to not being an expert on all things verilog (or anything in life for that mater), but I am trying to learn to parameterize a new module definition to expand its usefulne...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

The untypified string parameter seems to work however, see above.

The other question is, if e. g. VHDL string generics could be used with schematic entry drow-down selection for parameters, I did never see this feature in operation.