Do quratus2 gate-level simulation contain the interconnected delays？

Hi,

Quratus2 gate-level simulation only have gate delay or include all delays after placing and routing? Using Xilinx ISE, I know that there is RTL simulation(Behavioral Simulation), post-translation simulation(having gate delaypost), post-map simulation(I never used), post-route simulation(include all delays).

Thanks in advance.