Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Do not understand what toggle % truly means in Quartus PowerPlay Power Analyzer

I did some reading on this topic, but have not found the answer to my question. I do not understand what the “Toggle %” means in the Quartus PowerPlay Power Analyzer report (also provided in the "Simulation Files Read" in the Compilation Reports area within Quartus. I am using VCD data and selecting a start and end time. In the Altera Quartus II Handbook documentation, the following info is pretty much useless:

“Simulation Files Read

The Simulation Files Read section of the report lists the simulation output file that the .vcd used for power estimation. This section also includes the file ID, file type, entity, VCD start time, VCD end time, the unknown percentage, and the toggle percentage. The unknown percentage indicates the portion of the design module unused by the simulation vectors.” (from Quartus II Handbook Version 12.0 Volume 3: Verification, June 2012)

Searching some more, I came across this bit of info from the PowerPlay Early Power Estimator User Guide: Stratix, Stratix GX & Cyclone FPGAs (October 2005), which sounded reasonable:

“Toggle %

The average percentage of LEs toggling on each clock cycle. The toggle percentage ranges from 0 to 100%. Typically, the toggle percentage is 12.5%, which is the toggle percentage of a 16-bit counter. To be more conservative, you can use a higher toggle percentage.

For instance, a TFF with its input tied to VC C has a toggle rate of 100% because its output is changing logic states on every clock cycle. Figure 3–5 for an example. Figure 3–6 shows an example of a 4-bit counter. The first TFF with least significant bit ( LSB ) output cout0 has a toggle rate of 100% because cout0 toggles on every clock cycle. The toggle rate for the second TFF with output cout1 is 50% since cout1 only toggles on every two clock cycles. Consequently, the toggle rate for the third TFF with output cout2 and fourth TFF with output cout3 are 25% and 12.5%, respectively. Therefore, the average toggle percentage for this 4-bit counter is (100 + 50 + 25 + 12.5)/4 = 46.875%.”

Now, this would sit ok with me, but, in all of the cases where I ran PowerPlay on my designs using simulated data (with a start and stop time for the VCD), my Toggle % was easily over 46%. Most of my cases averaged around 70% - a far cry from the 12.5% default. Curious, I took the resulting Toggle % and re-run it by replacing the default value for the Default Rate Used for Remaining Signals in Quartus Settings for PowerPlay. This produced Toggle Rates FAR above what I got with simulated data – suggesting that the Toggle % provided by Quartus is not the same as the default value for the PowerPlay settings.

Can anybody clarify this?

thanjks

Can you explain or point me to better information on the topic of Toggle % reporting in Quartus PowerPlay?

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    I was using PowerPlay last week and also have trouble with getting reasonable numbers from Quartus.

    Attached is a PDF of measured power consumption from the DE0-nano board. The board was configured with a Qsys system containing a UART-to-Avalon-MM bridge and a slave interface to a power dissipation block. The power dissipation block contained either toggle registers or counters. The registers/counters could be enabled in blocks. The design had 128-bits of control, allowing power dissipation to be increased in ~1% steps. In the attached figure, 8-bits of registers were enabled for each step.

    The measurements reflect the fact that wider counters have lower average toggle rates, and hence lower average power dissipation.

    I tried getting Quartus (11.1sp1) to give me reasonable estimates on power dissipation, however, the toggle rates estimated for the counters were inconsistent with the measurements. I tried getting .VCD measurements for a large design, but after 10 hours of Modelsim-SE simulation time, I needed to use the PC for another job, so killed the simulation. I plan on revisiting this testing on a faster machine and on a DE4 in the next week or so.

    I know it doesn't really answer your questions, however, I wanted to let you know that you are not alone in your frustration :)

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Thanks for the reply,

    Looking at the signal activity file, if I interpret it correctly, the Toggle % refers to the number of nets that are toggling. If that is true, I have my question answered for the most part.

    That said, you bring up a good point that I am not sure about. I think I have a similar problem. I am running simulations on circuits with similar architectures that contain fewer gates and a lower toggle rate (MT/s) yet they consume more power than those with fewer toggles and more gates, which doesn't make sense.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    Looking at the signal activity file, if I interpret it correctly, the Toggle % refers to the number of nets that are toggling. If that is true, I have my question answered for the most part.

    --- Quote End ---

    The toggle rate is the number of transitions per clock period. A LSB of a counter has a 100% toggle rate, since it changes state every clock period.

    For a block of counters, Quartus should read a .VCD file, and get pretty close to (100%+50%+25%+12.5%)/4 = 46.75% for 4-bit counters, (100%+50%+25%+12.5%+6.25%+3.125%+1.5625%+0.78125%)/8 = 24.9% for 8-bit counters, and then 12.5% for 16-bit counters.

    --- Quote Start ---

    That said, you bring up a good point that I am not sure about. I think I have a similar problem. I am running simulations on circuits with similar architectures that contain fewer gates and a lower toggle rate (MT/s) yet they consume more power than those with fewer toggles and more gates, which doesn't make sense.

    --- Quote End ---

    I'd recommend testing in hardware if you can :)

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    As far as I've understood things it a fairly simple estimate of the % of your registers that will toggle on each clock edge.

    Ie in a module that has 1000 registers and a toggle % of 23.5% then 235 registers change state every clock cycle.

    I usually wind it up for safety but haven't had many power/temperature critical designs so am normally just checking my power supplies are up to the job.

    Nial.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Registers? Or nets in general? This morning, we took a look at the signal activity file and found that toggle % actually corresponds to the percentage of nodes that do not remain at a constant logic "0" or logic "1" during the sample time of the simulation (.vcd file) we presented.

    That said, I am not sure if the "toggle %" that can be specified in the Quartus PowerPlay Analyzer settings is the same value that appears in the *.pow.rpt Quartus outputs.