--- Quote Start ---
Looking at the signal activity file, if I interpret it correctly, the Toggle % refers to the number of nets that are toggling. If that is true, I have my question answered for the most part.
--- Quote End ---
The toggle rate is the number of transitions per clock period. A LSB of a counter has a 100% toggle rate, since it changes state every clock period.
For a block of counters, Quartus should read a .VCD file, and get pretty close to (100%+50%+25%+12.5%)/4 = 46.75% for 4-bit counters, (100%+50%+25%+12.5%+6.25%+3.125%+1.5625%+0.78125%)/8 = 24.9% for 8-bit counters, and then 12.5% for 16-bit counters.
--- Quote Start ---
That said, you bring up a good point that I am not sure about. I think I have a similar problem. I am running simulations on circuits with similar architectures that contain fewer gates and a lower toggle rate (MT/s) yet they consume more power than those with fewer toggles and more gates, which doesn't make sense.
--- Quote End ---
I'd recommend testing in hardware if you can :)
Cheers,
Dave
Honored Contributor
