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I am an beginner and thankful for every hint.
I hope I understand the concept of pipelining: Instead of calculating the mathematical expression or logic result at once, the output is produced over a range of FPGA cycles where. Why does latching the intermediate results and step-wise calculation increase the achievable clocking speed, fmax?
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The clock speed is determined by the worst case delay from one register to another. With less pipelining, there is more logic between the registers, and hence a larger delay/slower fmax.
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Back to the division: It would then be better practice if I invoke lpm_divide myself and connect the clock for pipelining? According to the manual lpm_divide megafunction supports pipelining.
About the '93 version: I am experiencing a very steep learning curve right now. Once I am more comfortable with the fixed-point integer arithmetic's etc., I might be able to handle my tasks without the fixed_pkg.
Thanks!
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Yes, invoking the divide yourself (either directly or from the megawizard - I suggest the latter at first) will give you a pipelined result. But even better to avoid divides as much as possible. Are you just trying to do A/B where B is constant? thats the same as A * 1/B, and 1/B is still a constant. Multiplies are much less resource hungry than divides, and need fewer pipe stages (usually just 1).
The fixed package is still a great thing to use and works really well. I used it for an entire image processing algorithm (it contained 2D filters, upsamplers, downsamplers and histograms).
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