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Remember that Quartus does not have full VHDL 2008 support yet, so using the '93 version will not carry any support from Altera.
Also, using divides like this is very poor practice - you get no pipelining so the FMax will be very low.
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I am an beginner and thankful for every hint.
I hope I understand the concept of pipelining: Instead of calculating the mathematical expression or logic result at once, the output is produced over a range of FPGA cycles where. Why does latching the intermediate results and step-wise calculation increase the achievable clocking speed, fmax?
Back to the division: It would then be better practice if I invoke lpm_divide myself and connect the clock for pipelining? According to the manual lpm_divide megafunction supports pipelining.
About the '93 version: I am experiencing a very steep learning curve right now. Once I am more comfortable with the fixed-point integer arithmetic's etc., I might be able to handle my tasks without the fixed_pkg.
Thanks!
Honored Contributor
