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VHDL 2008 adds the fixed point libraries that mean keeping track of fraction and integer separation in your words is really simple (integer bits have positive index values and fraction are negative, to match the 2^n offset). Otherwise you need to manually keep track of the separation (by using imarginary multiplication offsets etc).
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Tricky,
Software people mindset is geared to using fractional fixed point approach. FPGA engineers(old ones at least like myself) use fixed point as integer.
The fractional approach as you know is imaginary in the mind only. Actual values are bits and I prefer to "imagine" them as integers (also imaginary).
Manually keeping track of fraction is no problem at all and gives full visibility. Leaving that to tool such as fixed point library is an option but I find it very unnecessary and complicates type declaration when there is no problem to solve in the first place.
DSPBuilder is done by software guys and they do force sometimes their mindset but options are there and it just confuses and adds more confusion using both schemes. It also leads to bugs.
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