--- Quote Start ---
Hi!
I would like to divide a number by a set of constants (3, 5 or 7) and I have read in an old post that using a divider might be a waste of resources. I have also read that for simple divisions like the ones I need, it would be possible to use multipliers instead. I guess it would be something like this:
N = 14-bit numerator (the number I want to divide)
C = constant where C = {3, 5, 7}
Result = N*(1/C)
But I do not know how to get that 1/C in Verilog... Could anyone please give me an easy example? I would like to use an LPM_MULT so I would also like to know the optimal latency for a 178.2 MHz clock on an EP4CE10F17C8L FPGA. So far I have used an LPM_MULT to get a 14-bit result form a 10-bit and a 4-bit inputs and the latency is 2, but maybe I do not know if that would change in this case.
Thanks in advance!
--- Quote End ---
The concept is this:
suppose your input is x, coeff is y and you choose 14 bits resolution:
c = c * 2^n/2^n;
c = round(c*2^n)/2^n;
the term round(c*2^n) you precompute it, call it y, then in design you multiply:
x * y gives result, divide by 2^n i.e. discard n bits with/without rounding
Honored Contributor
